Nunja, es gibt durchaus einige tiefergehende Änderungen in der Art wie der Speicher verwendet und angesprochen wird... es gibt beispielsweise neue Befehle in der DDR4-Spec die es erlauben auf Bänke zuzugreifen bzw zumindest bereits zu adressieren obwohl sie noch in der Abarbeitung eines vorherigen Befehls stecken.
Aber ich bin wie gesagt selbst überrascht, dass diese Detailänderungen / Feintuning in der Art der Riegelansprache durchaus wenn auch sehr kleine aber messbare Effekte haben.
Was zusätzlich noch im Speichercontroller anders geregelt wird weiß wohl auch nur der Hersteller alleine, insgesamt gesehen ists aber tatsächlich so, dass DDR4 bei genau gleichem Takt und Latenzen minimal schneller als DDR3 ist.
Although it still operates in fundamentally the same way, DDR4 makes one major change to the command formats used by previous SDRAM generations. A new command signal /ACT is low to indicate the activate (open row) command.
The activate command requires more address bits than any other (18 row address bits in an 8 Gb part), so the standard /RAS, /CAS and /WE signals are shared with high-order address bits that are not used when /ACT is high. The combination of /RAS=L, /CAS=H and /WE=H that previously encoded an activate command is unused.
As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command.
In addition, A12 is used to request burst chop: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed.
Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.
In addition, there are three chip select signals (C0, C1, C2), allowing up to eight stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks).
The activate command requires more address bits than any other (18 row address bits in an 8 Gb part), so the standard /RAS, /CAS and /WE signals are shared with high-order address bits that are not used when /ACT is high. The combination of /RAS=L, /CAS=H and /WE=H that previously encoded an activate command is unused.
As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command.
In addition, A12 is used to request burst chop: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed.
Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.
In addition, there are three chip select signals (C0, C1, C2), allowing up to eight stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks).
Was zusätzlich noch im Speichercontroller anders geregelt wird weiß wohl auch nur der Hersteller alleine, insgesamt gesehen ists aber tatsächlich so, dass DDR4 bei genau gleichem Takt und Latenzen minimal schneller als DDR3 ist.
.gif "sm_B-) :-)")
