DKK007
PCGH-Community-Veteran(in)
AW: Intel-Prozessoren: Erneut Hinweise auf Sicherheitslücke
Von MeltDown ist Intel betroffen.
Spectre ist möglicherweise ein Designfehler in der "Out-Of-Order Execution" und trifft alle CPU Architekturen mit OOO-E. Also mindestens ARM und X86 mit allen Herstellern (inkl. AMD+Via). Wobei es ein paar Ausnahmen gibt, wo OOO-E bei billigen CPU Serien gestrichen wurde, z.B. die Atoms bis 2013.
Möglicherweise sind auch CPU Architekturen wie IBM PowerPC, Sparc oder Mips betroffen, die man heute nur noch in Vorlesungen zur technischen Informatik kennen lernt, die nutzen in neueren Version auch OOO-E.
Von MeltDown ist Intel betroffen.
Spectre ist möglicherweise ein Designfehler in der "Out-Of-Order Execution" und trifft alle CPU Architekturen mit OOO-E. Also mindestens ARM und X86 mit allen Herstellern (inkl. AMD+Via). Wobei es ein paar Ausnahmen gibt, wo OOO-E bei billigen CPU Serien gestrichen wurde, z.B. die Atoms bis 2013.
Möglicherweise sind auch CPU Architekturen wie IBM PowerPC, Sparc oder Mips betroffen, die man heute nur noch in Vorlesungen zur technischen Informatik kennen lernt, die nutzen in neueren Version auch OOO-E.
Wikipedia (Eng) zu Out-of-order execution: https://en.wikipedia.org/wiki/Out-of-order_execution#Micro-architectural_choicesWikipedia.org - Out-of-order execution schrieb:In 1990s, out-of-order execution became more common, and was featured in the IBM/MotorolaPowerPC 601 (1993), Fujitsu/HALSPARC64 (1995), IntelPentium Pro (1995), MIPSR10000 (1996), HPPA-8000 (1996), AMD K5 (1996) and DECAlpha 21264 (1998).
Notable exceptions to this trend include the SunUltraSPARC, HP/IntelItanium, Transmeta Crusoe, Intel Atom until Silvermont Architecture, and the IBMPOWER6.
[...]
Micro-architectural choices[edit]
IBM PowerPC processors use queues that are distributed among the different functional units while other out-of-order processors use a centralized queue. IBM uses the term reservation stations for their distributed queues.
- Are the instructions dispatched to a centralized queue or to multiple distributed queues?
Early Intel out-of-order processors use a results queue called a re-order buffer, while most later out-of-order processors use register maps.
- Is there an actual results queue or are the results written directly into a register file? For the latter, the queueing function is handled by register maps that hold the register renaming information for each instruction in flight.
More precisely: Intel P6 family microprocessors have both a re-order buffer (ROB) and a register alias table (RAT). The ROB was motivated mainly by branch misprediction recovery.
The Intel P6 family was among the earliest OoOE microprocessors, but were supplanted by the NetBurst architecture. Years later, Netburst proved to be a dead end due to its long pipeline that assumed the possibility of much higher operating frequencies. Materials were not able to match the design's ambitious clock targets due to thermal issues and later designs based on NetBurst, namely Tejas and Jayhawk, were cancelled. Intel reverted to the P6 design as the basis of the Core and Nehalem microarchitectures. The succeeding Sandy Bridge, Ivy Bridge, and Haswell microarchitectures are a departure from the reordering techniques used in P6 and employ re-ordering techniques from the EV6 and the P4 without a long pipeline.[SUP][7][/SUP]
Zuletzt bearbeitet:



