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Hier die Daten:
General Information
Processor Name: Intel Core i9-7940X
Original Processor Frequency: 3100.0 MHz
CPU ID: 00050654
CPU Brand Name: Intel(R) Core(TM) i9-7940X CPU @ 3.10GHz
CPU Vendor: GenuineIntel
CPU Stepping: M0
CPU Code Name: Skylake-X
CPU Technology: 14 nm
CPU S-Spec: SR3RQ
CPU Thermal Design Power (TDP): 165.0 W
CPU Power Limit 4 (PL4): 1023.9 W
CPU Power Limits (Max): Power = 363.00 W, Time = Unlimited
CPU Power Limit 1 - Long Duration: Power = Unlimited, Time = 1.00 sec [Unlocked]
CPU Power Limit 2 - Short Duration: Power = Unlimited, Time = 1.00 sec [Unlocked]
Configurable TDP Level 1 (Down): 165.00 W (31.50 W - Unlimited), 2400 MHz
Configurable TDP Level 2 (Up): 165.00 W (31.50 W - Unlimited), 2400 MHz
Current Configurable TDP Level: Nominal [Locked]
CPU Max. Junction Temperature (Tj,max): 110 °C
CPU Type: Production Unit
CPU Platform: Socket R4 (LGA2066)
Microcode Update Revision: 200004D
Favored Cores List: 9, 8, 1, 2, 11, 13, 3, 7, 5, 12, 6, 14, 10, 4
Number of CPU Cores: 14
Number of Logical CPUs: 28
Operating Points
CPU LFM (Minimum): 1200.0 MHz = 12 x 100.0 MHz
CPU HFM (Base): 3100.0 MHz = 31 x 100.0 MHz
CPU Turbo Max: 4400.0 MHz = 44 x 100.0 MHz [Unlocked]
Turbo Ratio Limits - IA/SSE, Fused: 44x (1-2c), 41x (3-4c), 40x (5-12c), 38x (13-14c)
Turbo Ratio Limits - IA/SSE, Resolved: 44x (1-2c), 41x (3-4c), 40x (5-12c), 38x (13-14c)
Turbo Ratio Limits - AVX2, Fused: 37x (1-2c), 35x (3-14c)
Turbo Ratio Limits - AVX2, Resolved: 37x (1-2c), 35x (3-14c)
Turbo Ratio Limits - AVX-512, Fused: 35x (1-2c), 33x (3-4c), 32x (5-12c), 31x (13-14c)
Turbo Ratio Limits - AVX-512, Resolved: 35x (1-2c), 33x (3-4c), 32x (5-12c), 31x (13-14c)
CPU Current: 1197.3 MHz = 12 x 99.8 MHz @ 0.7297 V
LLC/Ring Maximum: 2400.0 MHz = 24.00 x 100.0 MHz
LLC/Ring Current: 2394.5 MHz = 24.00 x 99.8 MHz
CPU Bus Type: Intel Direct Media Interface (DMI) v3.0
Maximum DMI Link Speed: 8.0 GT/s
Current DMI Link Speed: 8.0 GT/s
PCI-Express Current Clock: 99.8 MHz = 1.00 x 99.8 MHz
Number of Overclocking Bins: Unlimited
IA Overclocking
Voltage Offset: Supported
Voltage Override: Supported
Ratio Overclocking: Supported
Fused Ratio Limit: 80x
OC Ratio Limit: N/A
Voltage Mode: Interpolative
Voltage Offset: 0 mV
CLR (CBo/LLC/Ring) Overclocking
Voltage Offset: Supported
Voltage Override: Supported
Ratio Overclocking: Supported
Fused Ratio Limit: 80x
OC Ratio Limit: 80x
Voltage Mode: Interpolative
Voltage Offset: 0 mV
GT (Unslice) Overclocking
Voltage Offset: Supported
Voltage Override: Not Supported
Ratio Overclocking: Not Supported
Fused Ratio Limit: N/A
OC Ratio Limit: N/A
Voltage Mode: Interpolative
Voltage Offset: 0 mV
Cache and TLB
L1 Cache: Instruction: 14 x 32 KBytes, Data: 14 x 32 KBytes
L2 Cache: Integrated: 14 x 1 MBytes
L3 Cache: 19712 KBytes
Instruction TLB: 2MB/4MB Pages, Fully associative, 8 entries
Data TLB: 4 KB Pages, 4-way set associative, 64 entries
Standard Feature Flags
FPU on Chip Present
Enhanced Virtual-86 Mode Present
I/O Breakpoints Present
Page Size Extensions Present
Time Stamp Counter Present
Pentium-style Model Specific Registers Present
Physical Address Extension Present
Machine Check Exception Present
CMPXCHG8B Instruction Present
APIC On Chip / PGE (AMD) Present
Fast System Call Present
Memory Type Range Registers Present
Page Global Feature Present
Machine Check Architecture Present
CMOV Instruction Present
Page Attribute Table Present
36-bit Page Size Extensions Present
Processor Number Not Present
CLFLUSH Instruction Present
Debug Trace and EMON Store Present
Internal ACPI Support Present
MMX Technology Present
Fast FP Save/Restore (IA MMX-2) Present
Streaming SIMD Extensions Present
Streaming SIMD Extensions 2 Present
Self-Snoop Present
Multi-Threading Capable Present
Automatic Clock Control Present
IA-64 Processor Not Present
Signal Break on FERR Present
Virtual Machine Extensions (VMX) Present
Safer Mode Extensions (Intel TXT) Not Present
Streaming SIMD Extensions 3 Present
Supplemental Streaming SIMD Extensions 3 Present
Streaming SIMD Extensions 4.1 Present
Streaming SIMD Extensions 4.2 Present
AVX Support Present
Fused Multiply Add (FMA) Present
Carryless Multiplication (PCLMULQDQ)/GFMUL Present
CMPXCHG16B Support Present
MOVBE Instruction Present
POPCNT Instruction Present
XSAVE/XRSTOR/XSETBV/XGETBV Instructions Present
XGETBV/XSETBV OS Enabled Present
Float16 Instructions Present
AES Cryptography Support Present
Random Number Read Instruction (RDRAND) Present
Extended xAPIC Present
MONITOR/MWAIT Support Present
Thermal Monitor 2 Present
Enhanced SpeedStep Technology Present
L1 Context ID Not Present
Send Task Priority Messages Disabling Present
Processor Context ID Present
Direct Cache Access Present
TSC-deadline Timer Present
Performance/Debug Capability MSR Present
IA32 Debug Interface Support Present
64-Bit Debug Store Present
CPL Qualified Debug Store Present
Extended Feature Flags
64-bit Extensions Present
RDTSCP and TSC_AUX Support Present
1 GB large page support Present
No Execute Present
SYSCALL/SYSRET Support Present
Bit Manipulation Instructions Set 1 Present
Bit Manipulation Instructions Set 2 Present
Advanced Vector Extensions 2 (AVX2) Present
Advanced Vector Extensions 512 (AVX-512) Present
AVX-512 Prefetch Instructions Not Present
AVX-512 Exponential and Reciprocal Instructions Not Present
AVX-512 Conflict Detection Instructions Present
AVX-512 Doubleword and Quadword Instructions Present
AVX-512 Byte and Word Instructions Present
AVX-512 Vector Length Extensions Present
AVX-512 52-bit Integer FMA Instructions Not Present
Secure Hash Algorithm (SHA) Extensions Not Present
Software Guard Extensions (SGX) Support Not Present
Supervisor Mode Execution Protection (SMEP) Present
Supervisor Mode Access Prevention (SMAP) Present
Hardware Lock Elision (HLE) Present
Restricted Transactional Memory (RTM) Present
Memory Protection Extensions (MPX) Present
Read/Write FS/GS Base Instructions Present
Enhanced Performance String Instruction Present
INVPCID Instruction Present
RDSEED Instruction Present
Multi-precision Add Carry Instructions (ADX) Present
PCOMMIT Instructions Not Present
CLFLUSHOPT Instructions Present
CLWB Instructions Present
TSC_THREAD_OFFSET Present
Platform Quality of Service Monitoring (PQM) Present
Platform Quality of Service Enforcement (PQE) Present
FPU Data Pointer updated only on x87 Exceptions Present
Deprecated FPU CS and FPU DS Present
Intel Processor Trace Present
PREFETCHWT1 Instruction Not Present
AVX-512 Vector Bit Manipulation Instructions Not Present
AVX-512 Vector Bit Manipulation Instructions 2 Not Present
AVX-512 Galois Fields New Instructions Not Present
AVX-512 Vector AES Not Present
AVX-512 Vector Neural Network Instructions Not Present
AVX-512 Bit Algorithms Not Present
AVX-512 Carry-Less Multiplication Quadword (VPCLMULQDQ) Not Present
AVX-512 Vector POPCNT (VPOPCNTD/VPOPCNTQ) Not Present
User-Mode Instruction Prevention Not Present
Protection Keys for User-mode Pages Not Present
OS Enabled Protection Keys Not Present
Wait and Pause Enhancements (WAITPKG) Not Present
Total Memory Encryption Not Present
Read Processor ID Not Present
Cache Line Demote Not Present
MOVDIRI: Direct Stores Not Present
MOVDIR64B: Direct Stores Not Present
ENQCMD: Enqueue Stores Not Present
SGX Launch Configuration Not Present
AVX-512 BFLOAT16 Instructions Not Present
Enhanced Features
Thermal Monitor 1: Supported, Enabled
Thermal Monitor 2: Supported, Enabled
Enhanced Intel SpeedStep (GV3): Supported, Enabled
Bi-directional PROCHOT#: Enabled
Extended Auto-HALT State C1E: N/A
MLC Streamer Prefetcher Supported, Enabled
MLC Spatial Prefetcher Supported, Enabled
DCU Streamer Prefetcher Supported, Enabled
DCU IP Prefetcher Supported, Enabled
Intel Dynamic Acceleration (IDA) Technology: Not Supported
Intel Dynamic FSB Switching: Not Supported
Intel Turbo Boost Technology: Supported, Enabled
Programmable Ratio Limits: Supported, Disabled
Programmable TDC/TDP Limits: Supported, Disabled
Hardware Duty Cycling: Not Supported
CPU Scalable Features
ART (Always Running APIC Timer): Enabled
GSSE256 Instructions: Enabled
XSAVEOPT: Enabled
AES: Enabled
TSC Deadline: Enabled
SMI Inhibit with Opt-out SMM: Disabled
LT SX (TXT for Servers): Disabled
LT Production: Disabled
SMX: Disabled
VMX: Enabled
VT-x3: Enabled
Multi-Threading (HT): Enabled
LLC Ways: 0.5 M (4 lower ways)
Programmable TDP Limits: Enabled
Segment: HEDT (-X)
Scalable: No
Wayness: 1S
RAS Support: HEDT
Memory Frequency Support: Over-Clocking Supported
Physical Address Size Supported (Core): 46-bit
Soft SKU: Disabled
MC Mirror Mode: Disabled
PMEM WT: Disabled
PMEM: Disabled
DDRT (NVMDIMM): Disabled
2LM: Disabled
Maximum ADDDC Regions: Disabled
Extended APIC (x2APIC): Enabled
CPU HOT ADD: Disabled
GV3: Enabled
Core RAS (Data Poisoning, MCA Recovery): Disabled
TPH (TLP Processing Hint): Enabled
UPI Link 2: Disabled
UPI Link 1: Disabled
UPI Link 0: Disabled
Maximum Supported UPI speed: 9.6 GT/s
NTB: Disabled
PCIe Dual-Cast: Enabled
SRIS for independent PCIe clocking: Enabled
ECRC Check/Generate: Disabled
Live Error Recovery and RP IO Error: Disabled
Volume Management Device: Enabled
CBDMA Engine: Enabled
PCIe Mode on the DMI Port: Enabled
Patrol Scrub: Disabled
Rank Sparing: Disabled
UDIMM Support: Enabled
RDIMM Support: Enabled
DIR: Enabled
ECC: Disabled
QR DIMM: Enabled
Memory Channel 0: Enabled
Memory Channel 1: Enabled
Memory Channel 2: Disabled
Memory Channel 3: Enabled
Memory Channel 4: Enabled
Memory Channel 5: Disabled
CPU Stepping: M0
DRAM Power Meter: Enabled
DRAM RAPL: Enabled
Overclocking: Enabled
Energy Efficient Turbo: Enabled
Per-core P-states: Enabled
Uncore Frequency Scaling (UFS): Enabled
System Agent Power Management (SAPM) Dynamic Load Line (DLL): Enabled
Targeted SMI: Disabled
SMM CPU Save/Restore: Disabled
SMM Code Access Check: Disabled
Enhanced MCA: Disabled
FMA Instructions: Enabled
Hardware Lock Elison (HLE): Enabled
Hardware Lock Elison+ (HLE+)/RTM: Enabled
Cache Allocation Technology (CAT): Enabled
Cache Monitoring Technology (CMT): Enabled
Voltage Override Overclocking: Enabled
BCLK Coarse Ratio Support (PCIe Ratio Changing): Enabled
Physical Chop: High-Core Count (HCC)
VMCS Shadowing: Disabled
FIT Boot: Disabled
PFAT: Enabled
Error Spoofing: Disabled
Directory Cache: Enabled
Address based memory mirroring: Disabled
SKU Type: Internal
Autonomous C-State Control: Enabled
Hardware-Controlled Performance States (HWP): Enabled
Near Memory Caching for Persistent Memory: Disabled
Near Memory Caching for Far Memory: Disabled
Persistent Memory Capability: Disabled
Block Region Capability: Disabled
SXP MC Channel Mirroring Mode Capability: Disabled
DDR4 MC Channel Mirroring Mode Capability: Disabled
IIO to allocate in LLC: Enabled
Second IMC: Enabled
Maximum Memory Capacity: Unlimited
SVID Status: Enabled
Voltage Regulator (SVID)
VCCIN VR: IR/Infineon ASP1405I, VR13 (10mV VID)
VR Thermal Sensor: Supported
VCCSA VR: IR/Infineon ASP1405I, VR13 (5mV VID)
VR Thermal Sensor: Supported
Memory Ranges
Maximum Physical Address Size: 46-bit (64 TBytes)
Maximum Virtual Address Size: 48-bit (256 TBytes)
MTRRs
Range 0-1000000000 (0MB-65536MB) Type: Write Back (WB)
Range 1000000000-1080000000 (65536MB-67584MB) Type: Write Back (WB)
Range 1080000000-10A0000000 (67584MB-68096MB) Type: Write Back (WB)
Range 60000000-80000000 (1536MB-2048MB) Type: Uncacheable (UC)
Range 80000000-100000000 (2048MB-4096MB) Type: Uncacheable (UC)
Range 5F000000-60000000 (1520MB-1536MB) Type: Uncacheable (UC)